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MCP4725 bảng dữ liệu(PDF) 25 Page - Microchip Technology |
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MCP4725 bảng dữ liệu(HTML) 25 Page - Microchip Technology |
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25 / 50 page ![]() © 2009 Microchip Technology Inc. DS22039D-page 25 MCP4725 FIGURE 6-2: Write Commands for DAC Input Register and EEPROM. (A) Write DAC Register: (C2, C1, C0) = (0,1,0) or (B) Write DAC Register and EEPROM: (C2, C1, C0) = (0,1,1) 1st byte (Device Addressing) ACK (MCP4725) 2nd byte 3rd byte ACK (MCP4725) 4th byte D3 D2 D0 D1 1 1 0 0 A2 A1 A0 0 C2 C1 C0 X X PD1 PD0 X X X X X D11 D10 D9 D8 D7 D6 D5 D4 START Bit DAC Register Data (12 bits) STOP Bit Power Down Selection Unused Unused Unused Device Code Address Bits R/W Write Command Type: Write DAC Register: (C2 = 0, C1 = 1, C0 = 0) Write DAC Register and EEPROM: (C2 = 0, C1 = 1, C0 = 1). See Note 1 • The device updates the VOUT after this ACK pulse is issued. • For EEPROM Write: - The Charge Pump initiates the EEPROM writing sequence at the falling edge of this ACK pulse. - The RDY/BSY bit (pin) goes “low” at the falling edge of this ACK pulse and back to “high” immediately after the EEPROM write is completed. ACK (MCP4725) 2nd byte 3rd byte ACK (MCP4725) 4th byte D3 D2 D0 D1 C2 C1 C0 X X PD1 PD0 X X X X X D11 D10 D9 D8 D7 D6 D5 D4 STOP Bit Repeat Bytes of 2nd - 4th bytes Note 1: RDY/BSY bit stays “low” during the EEPROM write. Any new write command including repeat bytes during the EEPROM write mode is ignored. The RDY/BSY bit sets to “high” after the EEPROM write is completed. |
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