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STM32W108CBU63 bảng dữ liệu(PDF) 67 Page - STMicroelectronics |
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STM32W108CBU63 bảng dữ liệu(HTML) 67 Page - STMicroelectronics |
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67 / 179 page  STM32W108CB, STM32W108HB Serial interfaces Doc ID 16252 Rev 2 67/179 7.3.2 SPI configuration register (SCx_SPICFG) Address offset: 0xC858 (SC1_SPICFG) and 0xC058 (SC2_SPICFG) Reset value: 0x0000 0000 7.3.3 SPI status register (SCx_SPISTAT) Address offset: 0xC840 (SC1_SPISTAT) and 0xC040 (SC2_SPISTAT) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC_SPI RXDRV SC_S PIMS T SC_SP IRPT SC_SP IORD SC_SP IPHA SC_SP IPOL rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw [5] SC_SPIRXDRV: Receiver-driven mode selection bit (SPI master mode only). Clear this bit to initiate transactions when transmit data is available. Set this bit to initiate transactions when the receive buffer (FIFO or DMA) has space. [4] SC_SPIMST: Set this bit to put the SPI in master mode, clear this bit to put the SPI in slave mode. [3] SC_SPIRPT: This bit controls behavior on a transmit buffer underrun condition in slave mode. Clear this bit to send the BUSY token (0xFF) and set this bit to repeat the last byte. Changes to this bit take effect when the transmit FIFO is empty and the transmit serializer is idle. [2] SC_SPIORD: This bit specifies the bit order in which SPI data is transmitted and received. 0: Most significant bit first. 1: Least significant bit first. [1] SC_SPIPHA: Clock phase configuration: clear this bit to sample on the leading (first edge) and set this bit to sample on the second edge. [0] SC_SPIPOL: Clock polarity configuration: clear this bit for a rising leading edge and set this bit for a falling leading edge. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SC_SPI TXIDLE SC_SPI TXFREE SC_SPI RXVAL SC_SPI RXOVF rw rw rw rw rw rw rw rw rw rw rw rw r r r r [3] SC_SPITXIDLE: This bit is set when both the transmit FIFO and the transmit serializer are empty. |
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