STM32F107RC datasheet(49/95 Pages) STMICROELECTRONICS

49 / 95 page

STM32F105xx, STM32F107xx

Electrical characteristics

Doc ID 15274 Rev 4

49/95

All timings are derived from tests performed under ambient temperature and VDD supply

voltage conditions summarized in Table 9.

5.3.8

PLL, PLL2 and PLL3 characteristics

The parameters given in Table 27 and Table 28 are derived from tests performed under

temperature and VDD supply voltage conditions summarized in Table 9.

Table 26.

Low-power mode wakeup timings

Symbol

Parameter

Typ

Unit

tWUSLEEP

(1)

1. The wakeup times are measured from the wakeup event to the point in which the user application code

reads the first instruction.

Wakeup from Sleep mode

1.8

µs

tWUSTOP

(1)

Wakeup from Stop mode (regulator in run mode)

3.6

µs

Wakeup from Stop mode (regulator in low power mode)

5.4

tWUSTDBY

(1)

Wakeup from Standby mode

µs

Table 27.

PLL characteristics

Symbol

Parameter

Min(1)

1. Based on characterization, not tested in production.

Max(1)

Unit

fPLL_IN

PLL input clock(2)

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with

the range defined by fPLL_OUT.

312

MHz

Pulse width at high level

fPLL_OUT

PLL multiplier output clock

MHz

fVCO_OUT

PLL VCO output

144

MHz

tLOCK

PLL lock time

350

µs

Jitter

Cycle-to-cycle jitter

300

Table 28.

PLL2 and PLL3 characteristics

Symbol

Parameter

Min(1)

1. Based on characterization, not tested in production.

Max(1)

Unit

fPLL_IN

PLL input clock(2)

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with

the range defined by fPLL_OUT.

MHz

Pulse width at high level

fPLL_OUT

PLL multiplier output clock

MHz

fVCO_OUT

PLL VCO output

148

MHz

tLOCK

PLL lock time

350

µs

Jitter

Cycle-to-cycle jitter

400

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