MCP3202 datasheet(15/32 Pages) MICROCHIP

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DS21034E-page 15

MCP3202

4.0

DEVICE OPERATION

The MCP3202 A/D Converter employs a conventional

SAR architecture. With this architecture, a sample is

acquired on an internal sample/hold capacitor for

1.5 clock cycles starting on the second rising edge of

the serial clock after the start bit has been received.

Following this sample time, the input switch of the

converter opens and the device uses the collected

charge on the internal sample and hold capacitor to

produce a serial 12-bit digital output code. Conversion

rates of 100 ksps are possible on the MCP3202.

See Section 6.2

“Maintaining

Minimum

Clock

Speed”

for information on minimum clock rates.

Communication with the device is done using a 3-wire

SPI-compatible interface.

4.1

Analog Inputs

The MCP3202 device offers the choice of using the

analog input channels configured as two single-

ended inputs or a single pseudo-differential input.

Configuration is done as part of the serial command

before each conversion begins. When used in the

pseudo-differential

mode,

CH0

and

CH1

are

programmed as the IN+ and IN– inputs as part of the

command

string

transmitted

the

device.

The IN+ input can range from IN– to VREF (VDD + IN–).

The IN– input is limited to ±100 mV from the VSS rail.

The IN– input can be used to cancel small signal com-

mon-mode noise which is present on both the IN+ and

IN– inputs.

For the A/D Converter to meet specification, the charge

holding capacitor (CSAMPLE) must be given enough

time to acquire a 12-bit accurate voltage level during

the 1.5 clock cycle sampling period. The analog input

model is shown in Figure 4-1.

In this diagram, it is shown that the source impedance

(RS) adds to the internal sampling switch (RSS)

impedance, directly affecting the time that is required to

charge the capacitor, CSAMPLE. Consequently, larger

source impedances increase the offset, gain, and

integral linearity errors of the conversion.

Ideally, the impedance of the signal source should be

near zero. This is achievable with an operational

amplifier such as the MCP601 which has a closed loop

output impedance of tens of ohms. The adverse affects

of higher source impedances are shown in Figure 4-2.

When operating in the pseudo-differential mode, if the

voltage level of IN+ is equal to or less than IN–, the

resultant code will be 000h. If the voltage at IN+ is equal

to or greater than {[VDD + (IN–)] – 1 LSB}, then the

output code will be FFFh. If the voltage level at IN– is

more than 1 LSB below VSS, then the voltage level at

the IN+ input will have to go below VSS to see the 000h

output code. Conversely, if IN- is more than 1 LSB

above VSS, then the FFFh code will not be seen unless

the IN+ input level goes above VDD level.

4.2

Digital Output Code

The digital output code produced by an A/D Converter

is a function of the input signal and the reference

voltage. For the MCP3202, VDD is used as the

reference voltage. As the VDD level is reduced, the LSB

size is reduced accordingly. The theoretical digital

output code produced by the A/D Converter is shown

below.

EQUATION 4-1:

Digital Output Code

4096•V

-----------------------

where:

VIN

analog input voltage

VDD

supply voltage

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