Furthermore, it is a quite complex timing procedure to erase/program flash. Fortunately, the

MPC89x53A carried with convenient mechanism to help the user read/change the flash

content. Just filling the target address and data into several SFR, and triggering the built-in ISP

automation, the user can easily erase, read, and program the embedded flash and option

registers OR1.

There are several SFR designed to help the user implement the ISP functionality.

SFR: IFD (ISP Flash Data register):

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

(Data to be written into flash, or data got from flash)

IFD is the data port register for ISP operation. The data in IFD will be written into the desired address in

operating ISP write and it is the data window of readout in operating ISP read.

SFR: IFADRH (ISP Flash Address High):

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

(High byte of the address pointing to flash memory)

IFADRH is the high-byte address port for all ISP modes.

SFR: IFADRL (ISP Flash Address Low):

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

(Low byte of the address pointing to flash memory)

IFADRL is the low-byte address port for all ISP modes.

SFR: IFMT (ISP Flash Mode Table):

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

reserved

Mode Selection

Mode Selection

To Operate

0

0

0

Standby

0

0

1

AP-memory read

0

1

0

AP-memory/Data-flash program

0

1

1

AP-memory/Data-flash page erase

1

1

1

OR1 memory erase (IFADRL[0]=1).

1

0

1

OR1 memory read ( IFADRL[0] =1)

1

1

0

OR1 memory program ( IFADRL[0] = 1)

Note: OR0 cannot be changed by ISP operation. It can be accessed only by Writer. Only OR1 can be

changed by ISP program.

28

MPC89x53A Data Sheet

MEGAWIN