MPC82X52AS datasheet(17/72 Pages) MEGAWIN

17 / 72 page

MEGAWIN

MPC82x52A Data Sheet

{ISPAS1, ISPAS0}: = ISP-Address-Start

{0,0}: =

Set the ISP start address 1400H.

(ISP code could take 3K bytes)

{0,1}: =

Set the ISP start address 1800H.

(ISP code could take 2K bytes)

{1,0}: =

Set the ISP start address 1C00H.

(ISP code could take 1K bytes)

{1,1}: =

(default)

Express no ISP code.

HWBS: = HardWare-Boot-Selector

0: = (default)

Clearing the bit is to configure the device to boot from ISP program after power-up.

1:=

Setting the bit is to configure the device to boot normally from user’s application program

after power-up.

In fact, the boot entrance is determined by register SWBS from SFR ISPCR ignoring the boot

comes from RST-pin press, software-trigger, or power-up. However, if a boot happens and that

boot comes from power-up action, the device will first load the complement of the HWBS to SWBS,

and decides the boot entrance according to the state of bit SWBS. So the HWBS is named

HardWare Boot Selector. It influence on power-up boot, but not on the boot from RST-pin or

software-trigger.

reserved1:= The bit is reserved for afterward user, and should be left at set.

The user must not clear the bit; otherwise, there could be inadvertent effect impacted on

the device.

SB: = Used to decide if the program code will be Scrambled while it is dumped.

0: =

Code dump from Writer is scrambled.

1: = (default)

Code dump from Writer is transparent.

LOCK: = Used to decide if the program code will be Locked against the popular writer.

0: =

Code dumping from Writer is locked.

1: = (default)

Permit code dumping from general Writers.

NVM register: OR1 (Option Register 1):

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

OR1 [7:1]: = Used to set the boundary of IAP memory

The user’s application program can change only the IAP flash memory, neither of AP flash

memory itself, nor the ISP flash memory. The IAP memory is defined between address scope

OR1 [7:1]*512 and ISP-Address-Start.

Setting the OR1 [7:1] 1111111B means no IAP memory.

NVM register: OR2 (Option Register 2):

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

reserved1

OSCDN

reserved1

ENROSC

reserved1

reserved1:= The bit is reserved for afterward user, and should be left at set.

MPC82x52AS bảng dữ liệu(PDF) 17 Page - Megawin Technology Co., Ltd

MPC82x52AS bảng dữ liệu(HTML) 17 Page - Megawin Technology Co., Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

bảng dữ liệu tải về

Link URL