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XR16V698 bảng dữ liệu(PDF) 21 Page - Exar Corporation

tên linh kiện XR16V698
Giải thích chi tiết về linh kiện  2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
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XR16V698 bảng dữ liệu(HTML) 21 Page - Exar Corporation

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XR16V698
21
REV. 1.0.3
2.25V TO 3.6V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
2.16
Internal Loopback
Each UART channel provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 11
shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at HIGH or mark condition while RTS# and DTR# are de-asserted (HIGH),
and CTS#, DSR# CD# and RI# inputs are ignored.
FIGURE 11. INTERNAL LOOP BACK
TX [7:0]
RX [7:0]
RTS# [7:0]
MCR bit-4=1
VCC
VCC
VCC
Transmit Shift
Register
Receive Shift
Register
CTS# [7:0]
DTR# [7:0]
DSR# [7:0]
RI# [7:0]
CD# [7:0]
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#



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