công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

SMB239 bảng dữ liệu(PDF) 10 Page - Summit Microelectronics, Inc.

tên linh kiện SMB239
Giải thích chi tiết về linh kiện  Programmable Linear Battery Charger in 1.3 x 2.1 uCSP
PDF  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  SUMMIT [Summit Microelectronics, Inc.]
Trang chủ  http://www.summitmicro.com
Logo SUMMIT - Summit Microelectronics, Inc.

SMB239 bảng dữ liệu(HTML) 10 Page - Summit Microelectronics, Inc.

Back Button SMB239 Datasheet HTML 6Page - Summit Microelectronics, Inc. SMB239 Datasheet HTML 7Page - Summit Microelectronics, Inc. SMB239 Datasheet HTML 8Page - Summit Microelectronics, Inc. SMB239 Datasheet HTML 9Page - Summit Microelectronics, Inc. SMB239 Datasheet HTML 10Page - Summit Microelectronics, Inc. SMB239 Datasheet HTML 11Page - Summit Microelectronics, Inc. SMB239 Datasheet HTML 12Page - Summit Microelectronics, Inc. SMB239 Datasheet HTML 13Page - Summit Microelectronics, Inc. SMB239 Datasheet HTML 14Page - Summit Microelectronics, Inc. Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 30 page
background image
SMB239
Summit Microelectronics, Inc
2129 3.0 2/23/2009
10
I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 400 kHz
TA= 0°C to +70°C, VIN = +5.0V, VFLOAT = +4.2V unless otherwise noted. All voltages are relative to GND.
400kHz
Symbol
Description
Conditions
Min
Typ
Max
Units
fSCL
SCL clock frequency
0
400
kHz
TLOW
Clock low period
1.3
µs
THIGH
Clock high period
0.6
µs
tBUF
Bus free time between a STOP
and a START condition
Before new transmission – Note
3
1.3
µs
tSU:STA
Start condition setup time
0.6
µs
tHD:STA
Start condition hold time
0.6
µs
tSU:STO
Stop condition setup time
0.6
µs
tAA
Clock edge to data valid
SCL low to valid SDA (cycle n)
0.2
0.9
µs
tRDH
Data output hold time
SCL low (cycle n+1) to SDA
change
0.2
µs
tR
SCL and SDA rise time
Note 3
20 +
0.1Cb
300
ns
tF
SCL and SDA fall time
Note 3
20 +
0.1Cb
300
ns
tSU:DAT
Data in setup time
100
ns
tHD:DAT
Data in hold time
0
0.9
µs
TI
Noise filter SCL and SDA
Noise suppression
140
ns
tWR_CONFIG
Write cycle time config
Configuration registers
10
ms
tWR_EE
Write cycle time EE
Memory array
5
ms
Note 3: Guaranteed by Design.
Figure 4 – I
2C Timing Diagrams
t
R
t
F
t
HIGH
t
LOW
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
t
DH
t
AA
SCL
SDA
(IN)
SDA
(OUT)
t
WR (For Write Operation Only)
I2C TIMING DIAGRAMS



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com