SMB110 datasheet(16/34 Pages) SUMMIT

16 / 34 page

SMB110

Preliminary Information

Summit Microelectronics, Inc

2099 2.3 3/1/2005

Note: 1/ - Guaranteed by Design.

Figure 4 – I

2C timing diagram

I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS –100 kHz

(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)

100kHz

Symbol

Description

Conditions

Min

Typ

Max

Units

fSCL

SCL clock frequency

100

kHz

TLOW

Clock low period

4.7

µs

THIGH

Clock high period

4.0

µs

tBUF

Bus free time

Before new transmission - Note

4.7

µs

tSU:STA

Start condition setup time

4.7

µs

tHD:STA

Start condition hold time

4.0

µs

tSU:STO

Stop condition setup time

4.7

µs

tAA

Clock edge to data valid

SCL low to valid SDA (cycle n)

0.2

3.5

µs

tDH

Data output hold time

SCL low (cycle n+1) to SDA

change

0.2

µs

SCL and SDA rise time

Note 1/

1000

SCL and SDA fall time

Note 1/

300

tSU:DAT

Data in setup time

250

tHD:DAT

Data in hold time

Noise filter SCL and SDA

Noise suppression

100

tWR_CONFIG

Write cycle time config

Configuration registers

tWR_EE

Write cycle time EE

Memory array

TIMING DIAGRAMS

HIGH

LOW

SU:SDA

HD:SDA

SU:DAT

HD:DAT

SU:STO

BUF

SCL

SDA

(IN)

SDA

(OUT)

WR (For Write Operation Only)

TIMING DIAGRAMS

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