XRT86VL30 datasheet(13/62 Pages) EXAR

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XRT86VL30

REV. 1.0.3

T1/E1/J1 BITS ELEMENT - HARDWARE MANUAL

TxCHCLK

n/a

Transmit Channel Clock Output Signal (TxCHCLK):

The exact function of this pin depends on whether or not the

transmit framer enables the transmit fractional/signaling inter-

face to input fractional data, as described below.

If transmit fractional/signaling interface is disabled:

This pin indicates the boundary of each time slot of an out-

bound DS1/E1 frame. In T1 mode, this output pin is a 192kHz

clock which pulses "High" during the LSB of each 24 time

slots. In E1 mode, this output pin is a 256kHz clock which

pulses "High" during the LSB of each 32 time slots. The Ter-

minal Equipment can use this clock signal to sample the

TxCHN0 through TxCHN4 time slot identifier pins to deter-

mine which time slot is being processed.

If transmit fractional/signaling interface is enabled:

TxCHCLK is the fractional interface clock which either outputs

a clock signal for the time slot that has been configured to

input fractional data, or outputs an enable signal for the frac-

tional time slot so that fractional data can be clocked into the

device using the TxSERCLK pin.

NOTE:

Transmit fractional interface can be enabled by

programming to bit 4 - TxFr1544/TxFr2048 bit from

This pin is internally pulled "Low"

TRANSMIT SYSTEM SIDE INTERFACE

SIGNAL NAME

128-PIN# 80-PIN#

TYPE

OUTPUT

DRIVE(MA)

DESCRIPTION

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