| công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ADP3634ARDZ bảng dữ liệu(PDF) 7 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADP3634ARDZ bảng dữ liệu(HTML) 7 Page - Analog Devices |
|
7 / 16 page ![]() ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 Rev. A | Page 7 of 16 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SD 1 INA 2 PGND 3 INB 4 OTW 8 OUTA 7 VDD 6 OUTB 5 ADP3623/ ADP3633 TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECTLY CONNECTED TO ANY PIN OF THE PACKAGE, BUT IT IS ELECTRICALLY AND THERMALLY CONNECTED TO THE DIE SUBSTRATE, WHICH IS THE GROUND OF THE DEVICE. Figure 7. ADP3623/ADP3633 Pin Configuration Table 3. ADP3623/ADP3633 Pin Function Descriptions Pin No. Mnemonic Description 1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. 2 INA Inverting Input Pin for Channel A Gate Driver. 3 PGND Ground. This pin should be closely connected to the source of the power MOSFET. 4 INB Inverting Input Pin for Channel B Gate Driver. 5 OUTB Output Pin for Channel B Gate Driver. 6 VDD Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor. 7 OUTA Output Pin for Channel A Gate Driver. 8 OTW Overtemperature Warning Flag. Open drain, active low. SD 1 INA 2 PGND 3 INB 4 OTW 8 OUTA 7 VDD 6 OUTB 5 ADP3624/ ADP3634 TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD OF THE PACKAGE IS NOT DIRECTLY CONNECTED TO ANY PIN OF THE PACKAGE, BUT IT IS ELECTRICALLY AND THERMALLY CONNECTED TO THE DIE SUBSTRATE, WHICH IS THE GROUND OF THE DEVICE. Figure 8. ADP3624/ADP3634 Pin Configuration Table 4. ADP3624/ADP3634 Pin Function Descriptions Pin No. Mnemonic Description 1 SD Output Shutdown. When high, this pin disables normal operation, forcing OUTA and OUTB low. 2 INA Input Pin for Channel A Gate Driver. 3 PGND Ground. This pin should be closely connected to the source of the power MOSFET. 4 INB Input Pin for Channel B Gate Driver. 5 OUTB Output Pin for Channel B Gate Driver. 6 VDD Power Supply Voltage. Bypass this pin to PGND with a ~1 µF to 5 µF ceramic capacitor. 7 OUTA Output Pin for Channel A Gate Driver. 8 OTW Overtemperature Warning Flag. Open drain, active low. |
|
|
Link URL |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Liên kết đến bảng dữ liệu | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |