AD9548SLASHPCBZ datasheet(97/112 Pages) AD

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AD9548

Rev. 0 | Page 97 of 112

Address

Bits

Bit Name

Description

0A0F

[7]

Ref Mon Override DD

Overrides the reference monitor REF fault signal for Reference DD (default = 0, not

overridden).

[6]

Ref Mon Override D

Overrides the reference monitor REF fault signal for Reference D (default = 0, not

overridden).

[5]

Ref Mon Override CC

Overrides the reference monitor REF fault signal for Reference CC (default = 0, not

overridden).

[4]

Ref Mon Override C

Overrides the reference monitor REF fault signal for Reference C (default = 0, not

overridden).

[3]

Ref Mon Override BB

Overrides the reference monitor REF fault signal for Reference BB (default = 0, not

overridden).

[2]

Ref Mon Override B

Overrides the reference monitor REF fault signal for Reference B (default = 0, not

overridden).

[1]

Ref Mon Override AA

Overrides the reference monitor REF fault signal for Reference AA (default = 0, not

overridden).

[0]

Ref Mon Override A

Overrides the reference monitor REF fault signal for Reference A (default = 0, not

overridden).

0A10

[7]

Ref Mon Bypass DD

Bypasses the reference monitor for Reference DD (default = 0, not bypassed).

[6]

Ref Mon Bypass D

Bypasses the reference monitor for Reference D (default = 0, not bypassed).

[5]

Ref Mon Bypass CC

Bypasses the reference monitor for Reference CC (default = 0, not bypassed).

[4]

Ref Mon Bypass C

Bypasses the reference monitor for Reference C (default = 0, not bypassed).

[3]

Ref Mon Bypass BB

Bypasses the reference monitor for Reference BB (default = 0, not bypassed).

[2]

Ref Mon Bypass B

Bypasses the reference monitor for Reference B (default = 0, not bypassed).

[1]

Ref Mon Bypass AA

Bypasses the reference monitor for Reference AA (default = 0, not bypassed).

[0]

Ref Mon Bypass A

Bypasses the reference monitor for Reference A (default = 0, not bypassed).

1 See Figure 34 for details.

STATUS READBACK (REGISTER 0D00 TO REGISTER 0D19)

All bits in Register 0D00 to Register 0D19 are read only.

Table 130. EEPROM Status

Address

Bits

Bit Name

Description

0D00

[7:3]

Unused

[2]

Fault detected

An error occurred while saving data to or loading data from the EEPROM.

[1]

Load in progress

The control logic sets this bit while data is being read from the EEPROM.

[0]

Save in progress

The control logic sets this bit while data is being written to the EEPROM.

Table 131. SYSCLK Status

Address

Bits

Bit Name

Description

0D01

[7:5]

Unused

[4]

Stable

The control logic sets this bit when the device considers the system clock to be stable

(see the System Clock Stability Timer section).

[3:2]

Unused

[1]

Cal in progress

The control logic holds this bit set while the system clock calibration is in progress.

[0]

Lock detected

Indicates the status of the system clock PLL.

0 = unlocked.

1 = locked (or the PLL is disabled).

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