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CS61575-IL1Z bảng dữ liệu(PDF) 12 Page - Cirrus Logic |
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CS61575-IL1Z bảng dữ liệu(HTML) 12 Page - Cirrus Logic |
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12 / 34 page ![]() The E1 G.703 pulse shape is supported with line length selection LEN2/1/0=0/0/0. The pulse width will meet the G.703 pulse shape template shown in Figure 9, and specified in Table 4. The CS61574A and CS61575 will detect a static TCLK, and will force TTIP and TRING low to prevent transmission when data is not present. When any transmit control pin (TAOS, LEN0-2 or LLOOP) is toggled, the transmitter outputs will require approximately 22 bit periods to stabi- lize. The transmitter will take longer to stabilize when RLOOP is selected because the timing cir- cuitry must adjust to the new frequency. Transmit All Ones Select The transmitter provides for all ones insertion at the frequency of TCLK. Transmit all ones is se- lected when TAOS goes high, and causes continuous ones to be transmitted on the line (TTIP and TRING). In this mode, the TPOS and TNEG (or TDATA) inputs are ignored. If Remote Loopback is in effect, any TAOS request will be ignored. Receiver The receiver extracts data and clock from an AMI (Alternate Mark Inversion) coded signal and out- puts clock and synchronized data. The receiver is sensitive to signals over the entire range of ABAM cable lengths and requires no equalization or ALBO (Automatic Line Build Out) circuits. The signal is received on both ends of a center- tapped, center-grounded transformer. The transformer is center tapped on the IC side. The clock and data recovery circuit exceeds the jitter tolerance specifications of Publications 43802, 43801, AT&T 62411, TR-TSY-000170, and CCITT REC. G.823. Figure 9. Mask of the Pulse at the 2048 kbps Interface Ω Ω ± ± μ Table 4. CCITT G.703 Specifications CS61574A CS61575 12 DS154F3 -XO¶ &21),'(17,$/ |
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