DS641F2

15

CS8421

3. TYPICAL CONNECTION DIAGRAMS

CS8421

VD

VL

Serial

Audio

Source

ILRCK

ISCLK

SDIN

BYPASS

+2.5 V

+3.3 V or +5.0 V

0.1

μF0.1 μF

Serial

Audio

Input

Device

OLRCK

OSCLK

SDOUT

XTI

RST

SRC_UNLOCK

SAOF

TDM_IN

Hardware Control

Settings

GND

SAIF

MS_SEL

GND

**

1 k

Figure 5. Typical Connection Diagram, No External Master Clock

* When no external master clock is supplied to the part, both input and output must be set to Slave Mode for the

part to operate properly. This is done by connecting the MS_SEL pin to ground through a resistance of 0

Ω to 1 kΩ

+ 1% as stated in Table 1, “Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL),”

on page 19.

** The connection (VL or GND) and value of these two resistors determines the mode of operation for the input

and output serial ports as described in Table 2 on page 19 and Table 3 on page 19.