CS8421 datasheet(14/38 Pages) CIRRUS

14 / 38 page

DS641F2

CS8421

After powering up the CS8421, RST should be held low until the power supplies and clocks are settled.

The maximum possible sample rate is XTI/128.

OLRCK must remain high for at least 8 OSCLK periods in TDM Mode.

Only the input or the output serial port can be set as master at a given time.

Master Mode (Note 9)

I/OSCLK Frequency (non-TDM)

64*Fsi/o

MHz

OSCLK Frequency (TDM)

256*Fso

MHz

I/OLRCK Duty Cycle

I/OSCLK Duty Cycle

I/OSCLK Falling Edge to I/OLRCK Edge

tlcks

-5

OSCLK Falling Edge to OLRCK Edge (TDM)

tfss

-5

OSCLK Falling Edge to SDOUT Output Valid

tdpd

-7

SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge

tds

SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge

tdh

Parameters

Symbol

Min

Max

Units

OLRCK

(input)

sckh

sckl

fsh

fss

OSCLK

(input)

TDM_IN

(input)

SDOUT

(output)

MSB

dpd

MSB-1

MSB

MSB-1

lrckh

MSB

dpd

MSB-1

I/OLRCK

(input)

I/OSCLK

(input)

SDIN

(input)

SDOUT

(output)

MSB

MSB-1

sckh

sckl

lcks

lckd

Figure 1. Non-TDM Slave Mode Timing

Figure 2. TDM Slave Mode Timing

OLRCK

(output)

dpd

fss

OSCLK

(output)

TDM_IN

(input)

SDOUT

(output)

MSB

MSB-1

MSB

MSB-1

MSB

dpd

MSB-1

lcks

I/OLRCK

(output)

I/OSCLK

(output)

SDIN

(input)

SDOUT

(output)

MSB

MSB-1

Figure 3. Non-TDM Master Mode Timing

Figure 4. TDM Master Mode Timing

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