TMC22091 datasheet(13/60 Pages) CADEKA

13 / 60 page

PRODUCT SPECIFICATION

TMC22091/TMC22191

Control Register Deﬁnitions

Global Control Register (00)

Reserved

SRESET

PAL

LUMDIS

CHRDIS

HRESET

Reg

Bit

Name

Function

7-5

Reserved.

SRESET

Software reset. When LOW, resets and holds internal state machines and

disables outputs. When HIGH (normal), starts and runs state machines and

enables outputs.

PAL

Video standard select. When LOW, the NTSC standard is generated with 7.5

IRE pedestal. When HIGH, PAL standard video is generated. This bit is ignored

if Register 0E bit 7 is HIGH, enabling the 0E and 0F registers.

LUMDIS

Luminance input disable. When LOW (normal), luminance (Y) data from

external frame buffer is enabled. When HIGH, luminance (Y) data into the

TMC22x91 is forced to 0 IRE but sync pulses continue from the LUMA output.

CHRDIS

Chrominance input disable. When LOW (normal), burst and frame buffer data

into the TMC22x91 are enabled. when HIGH, burst and frame buffer data are

suppressed, enabling monochrome operation.

HRESET

Software reset enable. SRESET is forced LOW when the RESET pin is taken

LOW. State machines are reset and held. When HRESET is LOW, RESET may

be taken HIGH at any time. The TMC22x91 is enabled and a new frame is

begun with line 1, field 1 on the next PXCK after SRESET is set HIGH. The D/A

converters are powered down while RESET is LOW. When HRESET is HIGH,

a new frame is begun with line 1, field 1 on the next PXCK after RESET is taken

HIGH. SRESET is ignored. The D/A converters remain active during the reset

sequence.

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