TMC1203 datasheet(13/16 Pages) CADEKA

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PRODUCT SPECIFICATION

TMC1203

Segregate traces:

• A/D analog

• D/A analog

• Clocks

• Digital

Treat analog inputs as transmission lines. Cleanly route

traces over the ground plane bearing in mind that the

return currents will ﬂow through the ground plane

beneath the traces. Do not route digital traces nearby.

A few inches of digital trace less than a few line widths

from an analog trace will cross-couple noise into

adjacent analog circuits.

The power plane for the TMC1203 should be separate

from that which supplies the rest of the digital circuitry.

A single power plane should be used for all of the VDD

pins. If the power supply for the TMC1203 is the same

as that of the system's digital circuitry, power to the

TMC1203 should be decoupled with ferrite beads and

0.1

mF capacitors to reduce noise.

The ground plane should be solid, not cross-hatched.

Connections to the ground plane should have very short

leads.

Decoupling capacitors should be applied liberally to

VDD pins. Remember that not all power supply pins are

created equal. They supply different circuits on the inte-

grated circuit, each of which generate varying amounts

and types of noise. For best results, use 0.1

mF ceramic

capacitors. Lead lengths should be minimized. Ceramic

chip capacitors are the best choice.

If the digital power supply has a dedicated power plane

layer, it should not be placed under the TMC1203, the

voltage reference, or the analog inputs. Capacitive cou-

pling of digital power supply noise from this layer to the

TMC1203 and its related analog circuitry can have an

adverse effect on performance.

CLKX should be handled carefully. Jitter and noise on

this clock may degrade performance. Terminate the

clock line, if needed, to eliminate overshoot and ringing.

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