6

1/9/02

SPT8100

Figure 2a – Typical Interface Circuit

Mini-Circuit

T1-6T

Transformer

+A5V

+A3.3/5V

16

D0–15

Logic

Interfacing

Circuit

+D3.3/5V

+

0.1

0.1

SPT8100

FB1

1.0

1.43K

(50)

RDY

OVR

0.1

Gain Control

Output

Enable

(active Hi)

Clock

Input

+

10

0.1

1nF

4.7

10

+

10

GS2 GS1

GS0

OE

CLK

RS

Reset

.01

+

+

Figure 2b – Typical Interface Circuit

+

+A5V

+D3.3/5V

+

FB1

FB3

FB2

0.1

10

0.1

10

Mini-Circuit

T1-6T

Transformer

16

D0–15

Logic

Interfacing

Circuit

SPT8100

.01

1.43K

(50)

RDY

OVR

Gain Control

Output

Enable

(active Hi)

Clock

Input

+

10

0.1

1nF

OGND

GS2 GS1

GS0

OE

CLK

RS

Reset

1.0

+

0.1

4.7

+

Notes:

1. To avoid device latch-up, closely follow either figure 2a or 2b, depending on what is available in the system. The difference between figure 2a

and 2b is in the grounding.

2. FB = ferrite bead. FB1 must be placed as close to the device as possible.

5. Power supplies and references pins must have adequate decoupling. Surface-mount capacitors are highly recommended. The smallest value

of capacitors are to be placed as close to the pin as possible.

Ω

Ω

Ω

Ω

Ω)

–5

1.43

<2 MHz

–2

2.00

<2 MHz

–5

1.24

•2 MHz

–2

1.00

•2 MHz

800