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SPT7937

Figure 2 – Typical Interface Circuit

U1

(DUT)

+D3/5V

+

+

RGND

DGND

CLK

DGND

OGND

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D0

D12

1

28

(+4 V)

+A5

CLK IN

MSB

LSB

+D3/5V

FB

+

Notes:

1) Unless otherwise specified, all non-polarized capacitors are 0.01 microfarad

surface-mount chip capacitors. They need to be placed as close to the pin as possible

2) All polarized capacitors are 4.7 to 10 microfarad tantalum surface-mount capacitors

3) FB is a ferrite bead. Place FB as close to the DUT as possible

4) U1 is TOKO regulator TK11240B (4.0 V)

Out of Range Bit

AGND

+A5

+

10 F

+A5

+A5

TK11240B

U1

DGND

+D3/5

+

10 F

+D3/5

TYPICAL INTERFACE CIRCUIT

Very few external components are required to achieve the

stated device performance. Figure 2 shows the typical in-

terface requirements when using the SPT7937 in normal

circuit operation. The following sections provide descrip-

tions of the major functions and outline critical perfor-

mance criteria to consider for achieving the optimal device

performance.

POWER SUPPLIES AND GROUNDING

DD

from a single analog supply as shown in figure 2. A sepa-

rate digital supply should be used for the digital output

suggests using this power supply configuration to prevent

a possible latch-up condition on power up. In addition, the

power supplies must be powered up before the analog in-

put is applied.

) and all interface circuitry. CADEKA

CADEKA suggests that both the digital (DV

) and the ana-