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SPT7852

OPERATING DESCRIPTION

The general architecture for the CMOS ADC is shown in the

block diagram. The design contains two sets of eight identical

successive approximation ADC sections, all operating in par-

allel, a 16-phase clock generator, an 11-bit 8:1 digital output

multiplexer, correction logic, and a voltage reference genera-

tor which provides common reference levels for each ADC

section.

The high sample rate is achieved by using multiple SAR

ADC sections in parallel, each of which samples the input

signal in sequence. Each ADC uses 16 clock cycles to

complete a conversion. The clock cycles are allocated as

follows:

Table I – Clock Cycles

Clock

Operation

1

Reference zero sampling

2

Auto-zero comparison

3

Auto-calibrate comparison

4

Input sample

5–15

11-bit SAR conversion

16

Data transfer

The 16-phase clock, which is derived from the input clock,

synchronizes these events. The timing signals for adjacent

ADC sections are shifted by two clock cycles so that the

analog input is sampled on every other cycle of the input

clock by exactly one ADC section. After 16 clock periods,

the timing cycle repeats. The sample rate for the configura-

tion is one-half of the clock rate, e.g., for a 40 MHz clock

rate, the input sample rate is 20 MHz. The latency from ana-

log input sample to the corresponding digital output is 12

clock cycles.

• Since only sixteen comparators are used, a huge power

savings is realized.

• The auto-zero operation is done using a closed loop sys-

tem that uses multiple samples of the comparator's re-

sponse to a reference zero.

• The auto-calibrate operation, which calibrates the gain of

the MSB reference and the LSB reference, is also done

with a closed loop system. Multiple samples of the gain

error are integrated to produce a calibration voltage for

each ADC section.

• Capacitive displacement currents, which can induce sam-

pling error, are minimized since only one comparator per

• The total input capacitance is very low since sections of

the converter which are not sampling the signal are iso-

lated from the input by transmission gates.