SPT5240 datasheet(7/10 Pages) CADEKA

7 / 10 page

REV. 1 June 2003

SPT5240

DATA SHEET

Theory of Operation

The SPT5240 is a 10-bit 400 MWPS digital-to-analog

converter. It integrates a DAC core with a bandgap reference

and operates from a +3.3V power supply.

The DAC architecture is a compound differential current

output DAC consisting of a 6-bit fully segmented DAC for

the MSBs and a 4-bit fully segmented DAC for the LSBs.

The input cell, followed by a master-slave latch, buffers the

digital inputs. A 6:64 decoder decodes the digital data for

the MSBs, and a 4:16 decoder does so for the LSBs. The

outputs of the decoders are latched using a second bank

of master-slave latches whose outputs then drive differential

current switches, which steer the appropriate current to

the IOP or ION outputs.

The analog (AVDD) and digital (DVDD) power supplies are

separated on chip to allow ﬂexibility in the interface board.

The analog (AGND) and digital (DGND) are separated on

chip. Circuit board ground planes should be separated and

tied together with a ferrite bead.

tsettling

N+1

N-1

N+1

N-2

N+1

N+3

CLK

Digital

Inputs

VOP

1 LSB

VON

N+2

NOTE: Not to scale. For definition purposes only.

Figure 1: Timing Diagram

Pin Conﬁguration

Pin Assignments

Analog Outputs

IOP

DAC current output. Full-scale output at 11…11

input code.

ION

Complementary current output. Full-scale output

at 00…00 input code.

Digital Inputs

D0 – D9

Digital inputs (D0 = LSB).

PWD

Power down mode pin. Active high. Internally

pulled down.

CLK

Clock input pin. Data is latched on the rising edge.

Reference

ISET

Full-scale adjust control. Connection for

reference-current setting resistor.

Power

AGND

Analog Supply Ground.

DGND

Digital Supply Ground.

AVDD

Analog +3.3V supply.

DVDD

Digital +3.3V supply.

N/C

No Connect

CLK

AGND

DGND

SET

AGND

PWD

SPT5240SIT

32-pin LQFP

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