LTC4012-1 datasheet(12/28 Pages) LINER

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LTC4012/

LTC4012-1/LTC4012-2

4012f

OPERATION

Overview

The LTC4012 is a synchronous step-down (buck) current

mode PWM battery charger controller. The maximum

charge current is programmed by the combination of a

charge current sense resistor (RSENSE), matched input

resistors (RIN, Figure 1), and a programming resistor

(RPROG) between the PROG and GND pins. Battery

voltage is programmed with an external resistor divider

between FBDIV and GND (LTC4012) or two digital battery

voltage select pins (LTC4012-1/LTC4012-2). In addition,

the PROG pin provides a linearized voltage output of the

actual charge current.

The LTC4012 family does not have built-in charge

termination and is ﬂexible enough for charging any type

of battery chemistry. These are building block ICs intended

for use with an external circuit, such as a microcontroller,

capable of managing the entire algorithm required for

the speciﬁc battery being charged. Each member of the

LTC4012 family features a shutdown input and various state

indicator outputs, allowing easy and direct management by

a wide range of external (digital) charge controllers. Due

to the popularity of rechargeable Lithium-Ion chemistries,

the LTC4012-1 and LTC4012-2 also offer internal precision

resistors that can be digitally selected to produce one of

four preset output voltages for simpliﬁed design of those

charger types.

Shutdown

The LTC4012 remains in shutdown until DCIN is greater

than 5.1V and exceeds CLP by 60mV and SHDN is driven

above 1.4V. In shutdown, current drain from the battery

is reduced to the lowest possible level, thereby increasing

standby time. When in shutdown, the ITH pin is pulled to

GND and CHRG, ICL, FET gate drivers and INTVDD output

are all disabled. The charging can be stopped at any time

by forcing SHDN below 300mV.

AC Present Indication

The ACP status output correctly indicates sensed adapter

input voltage during all LTC4012 states. AC present is

indicated (ACP output low) as soon as DCIN exceeds

BAT by at least 500mV. Charging is not enabled until this

condition is ﬁrst met. After this event, charging is no longer

gated by AC present detection. If battery voltage rises due

to ESR, or DCIN droops due to current load, AC present

may no longer be indicated by the IC if charging was

started with very low input overhead. However, charging

will remain enabled unless DCIN falls below the supply

voltage on CLP.

Input PowerPath Control

The input PFET controller performs many important

functions. First, it monitors DCIN and enables the charger

when this input voltage is higher than the raw CLP system

supply. Next, it controls the gate of an external input

power PFET to maintain a low forward voltage drop when

charging, creating improved efﬁciency. It also prevents

reverse current ﬂow through this same PFET, providing

a suitable input blocking function. Finally, it helps avoid

synchronous boost operation during invalid operating

conditions by detecting elevated CLP voltage and forcing

the charger off.

If DCIN voltage is less than CLP, then DCIN must rise

60mV higher than CLP to enable the charger and activate

the ideal diode control. At this point, the ACPb status

output also transitions to low impedance to indicate

to the host system that an external adapter is present.

The gate of the input PFET is driven to a voltage sufﬁcient

to regulate a forward drop between DCIN and CLP of about

25mV. If the input voltage differential drops below this

point, the FET is turned off slowly. If the voltage between

DCIN and CLP drops to less than –25mV, the input FET is

turned off in less than 6μs to prevent signiﬁcant reverse

current from ﬂowing back through the PFET. In this case,

ACPb also switches back to high impedance and the

charger is disabled.

Soft-Start

Exiting the shutdown state enables the charger and releases

the ITH pin. When enabled, switching will not begin until

DCIN exceeds BAT by 500mV and ITH exceeds a threshold

that assures initial current will be positive (about 5% to

25% of the maximum programmed current). To limit inrush

current, soft-start delay is created with the compensation

values used on the ITH pin. Longer soft-start times can be

realized by increasing the ﬁlter capacitor on ITH, if reduced

loop bandwidth is acceptable. The actual charge current at

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