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STK22C48
Document Number: 001-51000 Rev. **
Page 8 of 14
AC Switching Characteristics
SRAM Read Cycle
Parameter
Description
25 ns
45 ns
Unit
Min
Max
Min
Max
Cypress
Parameter
Alt
tACE
tELQV
Chip Enable Access Time
25
45
ns
tRC
[6]
tAVAV, tELEH
Read Cycle Time
25
45
ns
tAA
[7]
tAVQV
Address Access Time
25
45
ns
tDOE
tGLQV
Output Enable to Data Valid
10
20
ns
tOHA
[7]
tAXQX
Output Hold After Address Change
5
5
ns
tLZCE
[8]
tELQX
Chip Enable to Output Active
5
5
ns
tHZCE
[8]
tEHQZ
Chip Disable to Output Inactive
10
15
ns
tLZOE
[8]
tGLQX
Output Enable to Output Active
0
0
ns
tHZOE
[8]
tGHQZ
Output Disable to Output Inactive
10
15
ns
tPU
[5]
tELICCH
Chip Enable to Power Active
0
0
ns
tPD
[5]
tEHICCL
Chip Disable to Power Standby
25
45
ns
Switching Waveforms
Figure 7. SRAM Read Cycle 1: Address Controlled [6, 7]
Figure 8. SRAM Read Cycle 2: CE and OE Controlled [6]
Notes
6. WE and HSB must be High during SRAM Read cycles.
7. Device is continuously selected with CE and OE both Low.
8. Measured ±200 mV from steady state output voltage.
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