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CY62148ESL MoBL®
Document #: 001-50045 Rev. **
Page 7 of 10
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [13, 14]
Figure 4. Read Cycle No. 2 (OE Controlled) [14, 15]
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [16, 17]
PREVIOUS DATA VALID
DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
IMPEDANCE
ICC
ISB
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
DATA VALID
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
ADDRESS
CE
WE
DATA IO
OE
NOTE 18
Notes
13. Device is continuously selected. OE, CE = VIL.
14. WE is HIGH for read cycles.
15. Address valid before or similar to CE transition LOW.
16. Data IO is high impedance if OE = VIH.
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
18. During this period, the IOs are in output state. Do not apply input signals.
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