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LE24L042CS bảng dữ liệu(PDF) 8 Page - Sanyo Semicon Device |
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LE24L042CS bảng dữ liệu(HTML) 8 Page - Sanyo Semicon Device |
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8 / 10 page ![]() LE24L042CS 7 EEPROM read operations 7-1. Current address reading The address equivalent to the memory address accessed last +1 is held as the internal address of the EEPROM for both write* and read operations. Therefore, provided that the master device has recognized the position of the EEPROM address pointer, data can be read from the memory address with the current address pointer without specifying the word address. As with writing, current address reading involves receiving the 7-bit device address and read command code “1” following the start condition, at which time the EEPROM generates an acknowledge signal. After this, the 8-bit data of the (n+1) address is output serially starting with the highest bits. After the 8 bits have been output, by not sending an acknowledge signal and inputting the stop condition, the EEPROM completes the read operation and is set to standby mode. If the previous read address is the last address, the address for the current address reading is rolled over to become address 0. *: If the write data is 1 or more bytes but less than 16 bytes, the current address after page writing is the address equivalent to the number of bytes to be written in the specified word address +1. If the write data is 16 or more bytes, it is the designated word address. If the last address (A3-A0=1111b) on the page has been designated by byte write as the word address, the first address (A3-A0=0000b) on the page serves as the internal address after writing. Device Address 0 1 0 1 R ACK NO ACK SDA D7 D6 D5 D4 D3 D2 D1 D0 Data(n+1) R/W S1 S2 A8 7-2. Random read Random read is a mode in which any memory address is specified and its data read. The address is specified by a dummy write input. First, when the EEPROM receives the 7-bit device address and write command code “0” following the start condition, it generates an acknowledge signal. It then receives the 8-bit word address, and generates an acknowledge signal. Through these operations, the word address is loaded into the address counter inside the EEPROM. Next, the start condition is input again and the current read is initiated. This causes the data of the word address that was input using the dummy write input to be output. If, after the data is output, an acknowledge signal is not sent and the stop condition is input, reading is completed, and the EEPROM returns to standby mode. D7 D6 - D1 D0 Data(n) Word Address(n) 0 1 0 1 W ACK ACK SDA A7 A6 A5 A4 A3 A2 A1 A0 Device Address 0 10 1 R ACK NO ACK Dummy Write Device Address Current Read R/W R/W S1 S2 A8 S1 S2 A8 7-3. Sequential read In this mode, the data is read continuously, and sequential read operations can be performed with both current address read and random read. If, after the 8-bit data has been output, acknowledge “0” is input and reading is continued without issuing the stop condition, the address is incremented, and the data of the next address is output. If acknowledge “0” continues to be input after the data has been output in this way, the data is successively output while the address is incremented. When the last address is reached, it is rolled over to address 0, and the data continues to be read. As with current address read and random read, the operation is completed by inputting the stop condition without sending an acknowledge signal. D7 D6 - D1 D0 Data(n) SDA Device Address 0 1 0 1 R ACK NO ACK D7 D6 - D1 D0 Data(n+1) ACK D7 D6 - D1 D0 Data(n+2) ACK D7 D6 - D1 D0 Data(n+x) ACK R/W S1 S2 A8 No.A1440-8/10 |
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