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TDF8599B bảng dữ liệu(PDF) 16 Page - NXP Semiconductors

tên linh kiện TDF8599B
Giải thích chi tiết về linh kiện  I2C-bus controlled dual channel 43 W/4 W, single channel 85 W/1 W class-D power amplifier with load diagnostics
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TDF8599B_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 29 July 2009
16 of 54
NXP Semiconductors
TDF8599B
I2C-bus controlled dual channel class-D power amplifier
• During the start-up sequence:
– When the TDF8599B is switched from standby to mute (td(stb-mute)). When a short
circuit on one of the output terminals (i.e. between VP or GND) is detected, the
start-up procedure is interrupted and the TDF8599B waits for open circuit outputs.
No large currents flow in the event of a short circuit to the supply lines because the
check is performed before the power stages are enabled.
• During operation:
–
A short to one of the supply lines activates OCP causing the amplifier channel to
shutdown. After 50 ms the amplifier channel restarts and WP is activated.
However, the corresponding amplifier channel will not start-up until the supply line
short circuit has been removed.
8.5.5 DC offset protection
DC offset Protection (DCP) is activated when the DC content in the demodulated output
voltage exceeds a set threshold (typically 2 V). DCP is active in both Mute mode and
Operating mode. Figure 14 shows how false triggering of the DCP by low frequencies in
the audio signal is prevented using the external capacitor (CF) to generate a cut-off
frequency.
In I2C-bus mode, DC offsets generate a voltage shift around the bias voltage. When the
voltage shift exceeds threshold values, the offset alarm bit DB1[D2] is set and if bit
IB1[D7] is not set, diagnostic information is also given. Any detected offset shuts down
both channels when bit IB2[D7] is not set. To restart the TDF8599B in I2C-bus mode, pin
EN must be toggled or DCP disabled by connecting pin DCP to pin AGND.
Fig 14. DC offset protection and diagnostic output
001aak078
OUT1P
OUT1N
V to I
OUT2P
OUT2N
DCP
DIAG
switch off channels
IB1[D6]
IB2[D6]
V to I
Vref
SQ
DB1[D2]
IB1[D7]
IB2[D7]
S4
50 k
Ω
S3
CF



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