TSB12C01APZ datasheet(10/59 Pages) TI

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1–4

1.4

Terminal Functions

Phy Interface

D0 – D7

CTL0

CTL1

LREQ

ISO

SCLK

DATA0 – DATA31

ADDR0 – ADDR7

INT

CYCLEIN

CYCLEOUT

BCLK

RESET

RAMEz

VCC

GND

Host

Bus

TSB12C01A

NTCLK

NTOUT

NTBIHIZ

CYST

CYDNE

GRFEMP

POWERON

Figure 1–1. TSB12C01A Terminal Functions

Table 1–1. Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

Host Bus Interface

ADDR0 –

ADDR7

22 – 25

27 – 30

Address 0 through address 7. Host bus address bus bits 0 through 7 that address

the quadlet-aligned FIFOs and configuration registers. The two least significant

address lines, 6 and 7, must be grounded.

Cycle acknowledge (active low). CA is a TSB12C01A control signal to the host bus.

When asserted (low), access to the configuration registers or FIFO is complete.

Cycle start (active low). CS is a host bus control signal to enable access to the

configuration registers or FIFO.

DATA0 –

DATA31

2–5

7–10

12 – 15

17 – 20

82 – 85

87 – 90

92 – 95

97 – 100

I/O

Data 0 through 31. DATA is a host bus data bus bits 0 through 31.

INT

Interrupt (active low). When INT is asserted (low), the TSB12C01A notifies the host

bus that an interrupt has occurred.

Read/write enable. When WR is deasserted (high) in conjunction with CS, a read

from the TSB12C01A is requested. When WR is asserted (low) in conjunction with

CS, a write to the TSB12C01A is requested.

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