TSB12C01A datasheet(43/59 Pages) TI

43 / 59 page

5–3

5.4

Host-Interface Timing Requirements, TA = 25°C (see Note 5)

PARAMETER

MIN

MAX

UNIT

tc1

Cycle time, BCLK (see Figure 6–1)

111

tw1(H)

Pulse duration, BCLK high (see Figure 6–1)

tw1(L)

Pulse duration, BCLK low (see Figure 6–1)

tsu1

Setup time, DATA0 – DATA31 valid before BCLK

↑ (see Figure 6–2)

th1

Hold time, DATA0 – DATA31 invalid after BCLK

↑ (see Figure 6–2)

tsu2

Setup time, ADDR0 – ADDR7 valid before BCLK

↑ (see Figures 6–2 and 6–3)

th2

Hold time, ADDR0 – ADDR7 invalid after BCLK

↑ (see Figures 6–2 and 6–3)

tsu3

Setup time, CS

↓ before BCLK↑ (see Figures 6–2 and 6–3)

th3

Hold time, CS

↑ after BCLK↑ (see Figures 6–2 and 6–3)

tsu4

Setup time, WR valid before BCLK

↑ (see Figures 6–2 and 6–3)

th4

Hold time, WR invalid after BCLK

↑ (see Figures 6–2 and 6–3)

NOTE 5: These parameters are not production tested.

5.5

Host-Interface Switching Characteristics Over Operating Free-Air

Temperature Range of 0

°C to 70°C, CL = 45 pF (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

td1

Delay time, BCLK

↑ to CA↓ (see Figure 6–2)

td2

Delay time, BCLK

↑ to CA↑ (see Figure 6–2)

td3

Delay time, BCLK

↑ to DATA0 – DATA31 valid (see Figure 6–3 and Note 5)

td4

Delay time, BCLK

↑ to DATA0 – DATA31 invalid (see Figure 6–3 and Note 5)

NOTE 5: These parameters are not production tested.

5.6

Phy-Interface Timing Requirements Over Operating Free-Air

Temperature Range of 0

°C to 70°C (see Note 5)

PARAMETER

MIN

MAX

UNIT

tc2

Cycle time, SCLK (see Figure 6–4)

20.24

20.45

tw2(H)

Pulse duration, SCLK high (see Figure 6–4)

tw2(L)

Pulse duration, SCLK low (see Figure 6–4)

tsu5

Setup time, D0 – D7 valid before SCLK

↑ (see Figure 6–6)

th5

Hold time, D0 – D7 invalid after SCLK

↑ (see Figure 6–6)

tsu6

Setup time, CTL0 – CTL1 valid before SCLK

↑ (see Figure 6–6)

th6

Hold time, CTL0 – CTL1 invalid after SCLK

↑ (see Figure 6–6)

NOTE 5: These parameters are not production tested.

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