TPS75201Q, TPS75215Q, TPS75218Q, TPS75225Q, TPS75233Q WITH RESET

TPS75401Q, TPS75415Q, TPS75418Q, TPS75425Q, TPS75433Q WITH POWER GOOD

FAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS242B – MARCH 2000 – REVISED JUNE 2003

5

POST OFFICE BOX 655303

TPS752xxQ RESET timing diagram

VI

Vres

(see Note A)

Vres

t

t

t

VO

Threshold

Voltage

RESET

Output

100 ms

Delay

100 ms

Delay

Output

Undefined

Output

Undefined

VIT +(see Note B)

VIT –(see Note B)

VIT –(see Note B)

VIT +(see Note B)

Less than 5% of the

output voltage

NOTES: A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards

for semiconductor symbology.

B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.