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PO100HSTL50A bảng dữ liệu(PDF) 2 Page - Potato Semiconductor Corporation |
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PO100HSTL50A bảng dữ liệu(HTML) 2 Page - Potato Semiconductor Corporation |
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2 / 8 page ![]() Copyright © Potato Semiconductor Corporation 2 Maximum Ratings DC Electrical Characteristics Symbol Description Test Conditions Min Typ Max Unit VOH Output High voltage Vcc=3V Vin=VIH or VIL, IOH= -12mA 2.4 3 - V VOL Output Low voltage Vcc=3V Vin=VIH or VIL, IOH=12mA - 0.3 0.5 V VIH Input High voltage Guaranteed Logic HIGH Level (Input Pin) 2 - Vcc V VIL Input Low voltage Guaranteed Logic LOW Level (Input Pin) -0.5 - 0.8 V IIH Input High current Vcc = 3.6V and Vin = Vcc - - 1 uA IIL Input Low current Vcc = 3.6V and Vin = 0V - - -1 uA VIK Clamp diode voltage Vcc = Min. And IIN = -18mA - -0.7 -1.2 V Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 3.3V, 25 °C ambient. 3. This parameter is guaranteed but not tested. 4. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 5. VoH = Vcc – 0.6V at rated current Description Max Unit Storage Temperature -65 to 150 °C Operation Temperature -40 to 85 °C Operation Voltage -0.5 to +4.6 V Input Voltage -0.5 to Vcc V Output Voltage -0.5 to Vcc+0.5 V Note: stresses greater than listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability specification is not implied. Pin Characteristics l o b m y S r e t e m a r a s P n o i t i d n o C t s e m T u m i n i M l a c i p y T m u m i x a M s t i n U C N I e c n a t i c a p a C t u p n I F 4 p R P U L L U P r o t s i s e R p u ll u P t B u p n I 88 88 K K Ω R N W O D L L U P r o t s i s e R n w o d ll u P t u A p n I Ω Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator PO100HSTL50A 04/19/09 Dual LVTTL/LVCMOS to Differential HSTL Translator |
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