September 2006

PCS2I9942C

rev 0.3

Low Voltage 1:18 Clock Distribution Chip

6 of 10

Notice: The information in this document is subject to change without notice.

()

()

[]

()

4

1

3

2

1

1

,

2

Equation

V

I

R

T

T

V

N

C

f

Equation

R

P

T

T

Equation

V

I

DC

V

V

I

DC

C

C

N

f

V

I

V

P

Equation

V

C

C

N

f

V

I

P

CC

CCQ

thja

A

MAX

J

CC

PD

CLOCKMAX

thja

TOT

A

J

P

OL

OL

Q

OH

CC

OH

Q

M

L

PD

CLOCK

CC

CCQ

CC

TOT

CC

M

L

PD

CLOCK

CC

CCQ

TOT

















⋅

−

−

⋅

⋅

⋅

=

⋅

+

=

⋅

⋅

−

+

−

⋅

+

























+

⋅

⋅

⋅

+

⋅

=

⋅

























+

⋅

⋅

⋅

+

=

∑

∑

∑

boards, using 2S2P boards will result in a lower thermal

impedance than indicated below.

Table 9. Thermal package impedance of the

32LQFP

Convection,

LFPM

board), °C/W

board), °C/W

Still air

86

61

100 lfpm

76

56

200 lfpm

71

54

300 lfpm

68

53

400 lfpm

66

52

500 lfpm

60

49

If the calculated maximum frequency is below 350 MHz, it

becomes the upper clock speed limit for the given

application conditions. The following eight derating charts

describe the safe frequency operation range for the

PCS2I9942C. The charts were calculated for a maximum

tolerable die junction temperature of 110

°C (120°C),

corresponding to an estimated MTBF of 9.1 years

(4 years), a supply voltage of 3.3V and series terminated

transmission line or capacitive loading. Depending on a

given set of these operating conditions and the available

device convection a decision on the maximum operating

frequency can be made.