November 2006

ASM2P2351AH

rev 0.3

1-Line To 10-Line Clock Driver With 3-State Outputs

6 of 12

Notice: The information in this document is subject to change without notice.

Figure 1. Load Circuit and Voltage Waveforms

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 3 10 MHz, ZO = 50Ω, tr 3 2.5 nS, tf 3 2.5 nS.

D. The outputs are measured one at a time with one transition per measurement.

3 V

0 V

3 V

1.5 V

1.5 V

1.5 V

0 V

1.5 V

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)