November 2006

ASM2P2310A

rev 0.3

2.5-V TO 3.3-V High-Performance Clock Buffer

3 of 11

Notice: The information in this document is subject to change without notice.

Function Table

Detailed Description

Output Enable Glitch Suppression Circuit

The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the clock input

such that the output buffer is enabled or disabled on the next full period of the input clock (negative edge triggered by the

input clock) (see Figure 1).

operation

.

a) Enable Mode

b) Disable Mode

Figure 1. Enable and Disable Mode Relative to CLK

↓

Input

Output

1G

2G

CLK

1Y[0:4]

2Y[0:4]

L

L

↓

L

L

H

L

↓

CLK

1

L

L

H

↓

L

CLK

1

H

H

↓

CLK

1

CLK

1

Note: 1 After detecting one negative edge on the CLK input, the output follows the input CLK if the control pin is held high.

CLK

CLK