TMS370 datasheet(13/63 Pages) TI

13 / 63 page

TMS370CxCx

8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

privileged operation and EEPROM write-protection override (continued)

Table 8. Privilege Bits

CONTROL BIT

NAME

LOCATION

CONTROL BIT

SCCR0

P010.5

P010.6

PF AUTO WAIT

OSC POWER

SCCR1

P011.2

P011.4

MEMORY DISABLE

AUTOWAIT DISABLE

SCCR2

P012.0

P012.1

P012.3

P012.4

P012.6

P012.7

PRIVILEGE DISABLE

INT1 NMI

CPU STEST

BUS STEST

PWRDWN / IDLE

HALT / STANDBY

T1PRI

P04F.6

P04F.7

T1 PRIORITY

TI STEST

SCIPRI

P05F.4

P05F.5

P05F.6

P05F.7

SCI ESPEN

SCIRX PRIORITY

SCITX PRIORITY

SCI STEST

ADPRI

P07F.5

P07F.6

P07F.7

AD ESPEN

AD PRIORITY

AD STEST

† The privilege bits are shown in a bold typeface in the peripheral file

frame 1 section.

low-power and IDLE modes

The TMS370CxCx devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For

mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the

time when the mask is manufactured.

The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping

the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes

is entered by executing the IDLE instruction when the PWRDWN / IDLE bit in SCCR2 has been set to 1. The

HALT / STANDBY bit in SCCR2 controls the low-power mode selection.

In the STANDBY mode (HALT / STANDBY = 0), all CPU activity and most peripheral module activity stops;

however, the oscillator, internal clocks, timer 1, and the receive-start bit detection circuit of the serial

communications interface 2 remain active. System processing is suspended until a qualified interrupt (hardware

RESET, external interrupt on INT1, timer 1 interrupt, or low level in the receive pin of the SCI2) is detected.

In the HALT mode (HALT / STANDBY = 1), the TMS370CxCx is placed in its lowest power-consumption mode.

The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is

suspended until a qualified interrupt (hardware RESET, external interrupt on the INT1, or low level on the receive

pin of the serial communications interface 2) is detected. The power-down mode selection bits are summarized

in Table 9.

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