TMS320VC5409GGU datasheet(39/89 Pages) TI

39 / 89 page

Functional Overview

April 1999 − Revised February 2004

SPRS082E

3.3.6 Peripheral Memory-Mapped Registers

The device provides a set of memory-mapped registers associated with peripherals. Table 3−4 gives a list of

CPU memory-mapped registers (MMRs) available on 5409. Table 3−16 shows additional peripheral MMRs

associated with the 5409.

Table 3−16. Peripheral Memory-Mapped Registers

NAME

ADDRESS

DESCRIPTION

TYPE

DRR20

20h

Data receive register 2

McBSP #0

DRR10

21h

Data receive register 1

McBSP #0

DXR20

22h

Data transmit register 2

McBSP #0

DXR10

23h

Data transmit register 1

McBSP #0

TIM

24h

Timer register

Timer

PRD

25h

Timer period counter

Timer

TCR

26h

Timer control register

Timer

–

27h

Reserved

SWWSR

28h

Software wait-state register

External Bus

BSCR

29h

Bank-switching control register

External Bus

–

2Ah

Reserved

SWCR

2Bh

Software wait-state control register

External Bus

HPIC

2Ch

HPI control register

HPI

–

2Dh−2Fh

Reserved

DRR22

30h

Data receive register 2

McBSP #2

DRR12

31h

Data receive register 1

McBSP #2

DXR22

32h

Data transmit register 2

McBSP #2

DXR12

33h

Data transmit register 2

McBSP #2

SPSA2

34h

McBSP2 subbank address register

McBSP #2

SPSD2

35h

McBSP2 subbank data register

McBSP #2

–

36−37h

Reserved

SPSA0

38h

McBSP0 subbank address register

McBSP #0

SPCD0

39h

McBSP0 subbank data register

McBSP #0

–

3Ah−3Bh

Reserved

GPIOCR

General-purpose I/O pins control register

GPIO

GPIOSR

General-purpose I/O pins status register

GPIO

–

3E−3F

Reserved

DRR21

40h

Data receive register 1

McBSP #1

DRR11

41h

Data receive register 2

McBSP #1

DXR21

42h

Data transmit register 1

McBSP #1

DXR11

43h

Data transmit register 2

McBSP #1

–

44h−47h

Reserved

SPSA1

48h

McBSP1 subbank address register

McBSP #1

SPCD1

49h

McBSP1 subbank data register

McBSP #1

–

4Ah−53h

Reserved

DMPREC

54h

DMA channel priority and enable control register

DMA

DMSA

55h

DMA subbank address register

DMA

DMSDI

56h

DMA subbank data register with autoincrement

DMA

DMSDN

57h

DMA subbank data registrer

DMA

CLKMD

58h

Clock mode register

PLL

–

59h−5Fh

Reserved

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