TMS320VC5410 datasheet(8/79 Pages) TI

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TMS320VC5410

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS075D – OCTOBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions (Continued)

TERMINAL

NAME

DESCRIPTION

I/O†

TERMINAL

NAME

DESCRIPTION

I/O†

MEMORY CONTROL SIGNALS (CONTINUED)

IAQ

O/Z

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address

bus and goes into the high-impedance state when OFF is low.

OSCILLATOR/TIMER SIGNALS

CLKOUT

O/Z

Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as

configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the

machine-cycle rate divided by 4.

CLKMD1

CLKMD2

CLKMD3

Clock mode select signals. CLKMD1 – CLKMD3 allows the selection and configuration of different clock modes

such as crystal, external clock, PLL mode.

X2/CLKIN

Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input.

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left

unconnected. X1 does not go into the high-impedance state when OFF is low.

TOUT

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT

cycle wide. TOUT also goes into the high-impedance state when OFF is low.

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),

AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS

BCLKR0

BCLKR1

BCLKR2

I/O/Z

Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.

BDR0

BDR1

BDR2

Serial data receive input

BFSR0

BFSR1

BFSR2

I/O/Z

Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.

BCLKX0

BCLKX1

BCLKX2

I/O/Z

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as

an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state when

OFF goes low.

BDX0

BDX1

BDX2

O/Z

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is

asserted, or when OFF is low.

BFSX0

BFSX1

BFSX2

I/O/Z

Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over

BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes

into the high-impedance state when OFF is low.

BCLKS0

BCLKS1

BCLKS2

Serial port clock reference. The McBSP can be programmed to use either BCLKS or the CPU clock as a

reference for generation of internal clock and frame sync signals. Pins with internal pullup devices.

NOTE: These pins are not available on the PGE package.

MISCELLANEOUS SIGNAL

No connection

HOST-PORT INTERFACE SIGNALS

HD0–HD7

I/O/Z

Parallel bidirectional data bus. HD0–HD7 is placed in the high-impedance state when not outputting data. The

signals go into the high-impedance state when OFF is low. The HPI data bus has a feature called a bus holder

that eliminates passive components and the power dissipation associated with them. The bus holder keeps the

data bus at the previous logic level when the bus goes into high-impedance state. The bus holder on the HPI

data bus can be enabled/disabled under software control.

† I = Input, O = Output, Z = High-impedance, S = Supply

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