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TMS320UVC5402 bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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TMS320UVC5402 bảng dữ liệu(HTML) 1 Page - Texas Instruments |
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1 / 60 page  TMS320UVC5402 FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS100A – APRIL 1999 – REVISED AUGUST 1999 1 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 D Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus D 40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators D 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation D Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator D Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle D Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs) D Data Bus With a Bus-Holder Feature D Extended Addressing Mode for 1M × 16-Bit Maximum Addressable External Program Space D 4K x 16-Bit On-Chip ROM D 16K x 16-Bit Dual-Access On-Chip RAM D Single-Instruction-Repeat and Block-Repeat Operations for Program Code D Block-Memory-Move Instructions for Efficient Program and Data Management D Instructions With a 32-Bit Long Word Operand D Instructions With Two- or Three-Operand Reads D Arithmetic Instructions With Parallel Store and Parallel Load D Conditional Store Instructions D Fast Return From Interrupt D On-Chip Peripherals – Software-Programmable Wait-State Generator and Programmable Bank Switching – On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source – Two Multichannel Buffered Serial Ports (McBSPs) – Enhanced 8-Bit Parallel Host-Port Interface (HPI-8) – Two 16-Bit Timers – Six-Channel Direct Memory Access (DMA) Controller D Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes D CLKOUT Off Control to Disable CLKOUT D On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1† (JTAG) Boundary Scan Logic D 33-ns Single-Cycle Fixed-Point Instruction Execution Time (30 MIPS) D 1.2-V Core Power Supply D 1.2-V to 2.75-V I/O Power Supply Enables Operation With a Single 1.2-V Supply or With Dual Supplies D Available in a 144-Pin Plastic Thin Quad Flatpack (TQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix) description The TMS320UVC5402 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UVC5402 unless otherwise specified) is the industry’s first 1.2-V DSP. This processor offers ultra low power consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage enables it to operate with a single 1.2-V power supply or with dual power supplies for mixed voltage systems. This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V systems. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1999, Texas Instruments Incorporated † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
Số phần tương tự - TMS320UVC5402 |
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Mô tả tương tự - TMS320UVC5402 |
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