TMS320F243 datasheet(33/116 Pages) TI

33 / 116 page

TMS320F243, TMS320F241

DSP CONTROLLERS

SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

interrupt operation sequence (continued)

The PIE controller decodes the PAB value and generates an internal peripheral interrupt acknowledge to

load the PIV into the PIVR. The appropriate peripheral interrupt vector (or the phantom interrupt vector),

is referenced from the table stored in the PIE controller.

When the GISR has completed any necessary context saves, it reads the PIVR and uses the interrupt vector

as a target (or to generate a target) for a branch to the Event-Specific Interrupt Service Routine (SISR) for

the interrupt event which occurred in the peripheral. Interrupts

must not be re-enabled until the PIVR has

been read; otherwise, its contents can get overwritten by a subsequent interrupt.

external interrupts

The ’F243/’F241 devices have four external interrupts. These interrupts include:

D XINT1. The XINT1 control register (at 7070h) provides control and status for this interrupt. XINT1 can be used

as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a general-purpose I/O pin. XINT1

can also be programmed to trigger an interrupt on either the rising or the falling edge.

D XINT2. The XINT2 control register (at 7071h) provides control and status for this interrupt. XINT2 can be used

as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or a general-purpose I/O pin. XINT2 can

also be programmed to trigger an interrupt on either the rising or the falling edge.

D NMI. This is a nonmaskable external interrupt.

D PDPINT. This interrupt is provided for safe operation of power converters and motor drives controlled by

the ’F243/’F241. This maskable interrupt can put the timers and PWM output pins in high-impedance states

and inform the CPU in case of motor drive abnormalities such as overvoltage, overcurrent, and excessive

temperature rise. PDPINT is a Level 1 interrupt.

Table 11 is a summary of the external interrupt capability of the ’F243/’F241.

Table 11. External Interrupt Types and Functions

EXTERNAL

INTERRUPT

CONTROL

NAME

CONTROL

ADDRESS

MASKABLE?

XINT1

XINT1CR

7070h

Yes

(Level 1 or 6)

XINT2

XINT2CR

7071h

Yes

(Level 1 or 6)

NMI

—

PDPINT

EVIMRA

742Ch

Yes

(Level 1)

TMS320F243 bảng dữ liệu(PDF) 33 Page - Texas Instruments

TMS320F243 bảng dữ liệu(HTML) 33 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL