TMS320C6201 datasheet(39/75 Pages) TI

39 / 75 page

TMS320C6201, TMS320C6201B

DIGITAL SIGNAL PROCESSORS

SPRS051F – JANUARY 1997 – REVISED AUGUST 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK)

(see Figure 17) (’C6201B)

’C6201B-200

’C6201B-233

UNIT

NO.

MIN

MAX

MIN

MAX

UNIT

tsu(EDV-SSCLKH)

Setup time, read EDx valid before SSCLK high

2.5

1.1

th(SSCLKH-EDV)

Hold time, read EDx valid after SSCLK high

1.5

switching characteristics for synchronous-burst SRAM cycles† (half-rate SSCLK)

(see Figure 17 and Figure 18) (’C6201B)

PARAMETER

’C6201B-200

’C6201B-233

UNIT

NO.

PARAMETER

MIN

MAX

MIN

MAX

UNIT

tosu(CEV-SSCLKH)

Output setup time, CEx valid before SSCLK high

1.5P – 3

1.5P – 2.2

toh(SSCLKH-CEV)

Output hold time, CEx valid after SSCLK high

0.5P – 1.5

0.5P – 1.1

tosu(BEV-SSCLKH)

Output setup time, BEx valid before SSCLK high

1.5P – 3

1.5P – 2.2

toh(SSCLKH-BEIV)

Output hold time, BEx invalid after SSCLK high

0.5P – 1.5

0.5P – 1.1

tosu(EAV-SSCLKH)

Output setup time, EAx valid before SSCLK high

1.5P – 3

1.5P – 2.2

toh(SSCLKH-EAIV)

Output hold time, EAx invalid after SSCLK high

0.5P – 1.5

0.5P – 1.1

tosu(ADSV-SSCLKH)

Output setup time, SSADS valid before SSCLK

high

1.5P – 3

1.5P – 2.2

toh(SSCLKH-ADSV)

Output hold time, SSADS valid after SSCLK high

0.5P – 1.5

0.5P – 1.1

tosu(OEV-SSCLKH)

Output setup time, SSOE valid before SSCLK

high

1.5P – 3

1.5P – 2.2

toh(SSCLKH-OEV)

Output hold time, SSOE valid after SSCLK high

0.5P – 1.5

0.5P – 1.1

tosu(EDV-SSCLKH)

Output setup time, EDx valid before SSCLK high

1.5P – 3

1.5P – 2.2

toh(SSCLKH-EDIV)

Output hold time, EDx invalid after SSCLK high

0.5P – 1.5

0.5P – 1.1

tosu(WEV-SSCLKH)

Output setup time, SSWE valid before SSCLK

high

1.5P – 3

1.5P – 2.2

toh(SSCLKH-WEV)

Output hold time, SSWE valid after SSCLK high

0.5P – 1.5

0.5P – 1.1

† When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

For CLKMODE x1:

1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.

0.5P = PL, where PL = pulse duration of CLKIN low.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

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