TMS320C242FN datasheet(23/66 Pages) TI

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TMS320C242

DSP CONTROLLER

SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

clock generation

The ’C242 device has an on-chip, (x4) PLL-based clock module. This module provides all the necessary

clocking signals for the device, as well as control for low-power mode entry. The only external component

necessary for this module is a fundamental crystal. The “times 4” (x4) option for the ’C242 PLL is fixed and

cannot be changed.

The PLL-based clock module provides two modes of operation:

D Crystal-operation

This mode allows the use of a 5-MHz external reference crystal/resonator to provide the time base to the

device.

D External clock source operation

This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external

clock source input on the XTAL1/CLKIN pin. In this case, an external oscillator clock is connected to the

XTAL1/CLKIN pin.

The clock module includes two external pins:

XTAL1/CLKIN

clock source/crystal input

XTAL2

output to crystal

XTAL2

XTAL1/CLKIN

PLL

XTAL

OSC

CPUCLK

Figure 6. PLL Clock Module Block Diagram

low-power modes

The ’24x has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the CPU,

but the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down to

save power while the peripherals (clocked with CLKOUT) continue to run. The CPU exits the IDLE state if it is

reset, or, if it receives an interrupt request.

clock domains

All ’24x-based devices have two clock domains:

CPU clock domain – consists of the clock for most of the CPU logic

System clock domain – consists of the peripheral clock (which is derived from CLKOUT of the CPU) and

the clock for the interrupt logic in the CPU.

When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues

to run. This mode is also known as IDLE1 mode. The ’24x CPU also contains support for a second IDLE mode,

IDLE2. By asserting IDLE2 to the ’24x CPU, both the CPU clock domain and the system clock domain are

stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the

oscillator and WDCLK are also shut down when in IDLE2 mode.

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