TMS320 datasheet(24/69 Pages) TI

24 / 69 page

TMS32020

SPRS010B — MAY 1987 — REVISED NOVEMBER 1990

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77001

MEMORY AND PERIPHERAL INTERFACE TIMING

switching characteristics over recommended operating conditions (see Note 3)

PARAMETER

MIN

TYP

MAX

UNIT

td(C1-S)

STRB from CLKOUT1 (if STRB is present)

Q – 15

Q + 15

td(C2-S)

CLKOUT2 to STRB (if STRB is present)

– 15

tsu(A)

Address setup hold time before STRB low (see Note 5)

Q – 30

th(A)

Address hold time after STRB high (see Note 5)

Q – 15

tw(SL)

STRB low pulse duration (no wait states, see Note 6)

tw(SH)

STRB high pulse duration (between consecutive cycles, see Note 6)

tsu(D)W

Data write setup time before STRB high (no wait states)

2Q – 45

th(D)W

Data write hold time from STRB high

Q – 15

ten(D)

Data bus starts being driven after STRB low (write cycle)

0†

tdis(D)

Data bus three-state after STRB high (write cycle)

Q+30†

td(MSC)

MSC valid from CLKOUT1

–25

† Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.

6. Delays between CLKOUT1/CLKOUT2 edges and STRB edges track each other, resulting in tw(SL) and tw(SH) being 2Q with

no wait states.

timing requirements over recommended operating conditions (see Note 3)

MIN

NOM

MAX

UNIT

ta(A)

Read data access time from address time (read cycle, see Notes 5 and 7)

3Q – 70†

tsu(D)R

Data read setup time before STRB high

th(D)R

Data read hold time from STRB high

td(SL-R)

READY valid after STRB low (no wait states)

Q – 40

td(C2H-R)

READY valid after CLKOUT2 high

Q – 40

th(SL-R)

READY hold time after STRB low (no wait states)

Q – 5

th(C2H-R)

READY hold after CLKOUT2 high

Q – 5

td(M-R)

READY valid after MSC valid

2Q – 50

th(M-R)

READY hold time after MSC valid

† Value derived from characterization data and not tested.

NOTES: 3. Q = 1/4tc(C).

5. A15-A0, PS, DS, IS, R/W, and BR timings are all included in timings referenced as “address”.

7. Read data access time is defined as ta(A) = tsu(A) + tw(SL) – tsu(D)R.

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