TLV987

3-V 10-BIT 27 MSPS AREA CCD SENSOR

SIGNAL PROCESSOR

SLAS211A – MARCH 1999 – REVISED SEPTEMBER 1999

13

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

CDS/PGA signal processor

The output from the CCD sensor is first fed to a correlated double sampler (CDS). The CCD signal is sampled

and held during the reset reference interval and the video signal interval. By subtracting two resulting voltage

levels, the CDS removes low-frequency noise from the output of the CCD sensor and obtains the voltage

difference between the CCD reference level and the video level of each pixel. Two sample and hold control

pulses (SR and SV) are required to perform the CDS function.

The CCD output is capacitively coupled to the TLV987. The ac coupling capacitor is clamped to establish proper

dc bias during the dummy pixel interval by the CLAMP input. The bias at the input to the TLV987 is set to 1.3

V. Normally, CLAMP is applied at the sensor’s line rate. A capacitor, with a value ten times larger than that of

the input ac coupling capacitor, should be connected between the CLREF pin and the AGND pin.

When operating the TLV987 at its maximum speed, the CCD internal source resistance should be smaller than

50

Ω. Otherwise, CCD output buffering is required.

The signal is sent to the PGA after the CDS function is complete. The PGA gain can be adjusted from 0 dB to

36 dB by programming the internal gain register via the serial port. The PGA is digitally controlled with 9-bit

resolution on a linear dB scale, resulting in a 0.09-dB gain step. The gain can be expressed by the following

equation:

Gain = PGA code

× 0.09375 dB

Where, the PGA code has a range of 0 to 383.

For example, if the PGA code = 64, then the PGA gain = 6 dB (or gain of 2)

The TLV987 has direct access to the PGA outputs through the TPP pin and the TPM pin. See

test register

description paragraph for details.

ADC

The ADC employs a pipelined architecture to achieve high throughput and low power consumption. Fully

differential implementation and digital error correction ensure 10-bit resolution.

The latency of the ADC data output is 4.5 ADCCLK cycles as shown in Figure 2. Pulling the OE pin (pin 24) high

puts the ADC output in high impedance.

user DACs

The TLV987 includes two user DACs that can be used for external analog settings. The output voltage of each

DAC can be independently set and has a range of 0 V to the supply voltage with 8-bit resolution. When the user

DACs are not used in a camera system, they can be put in the standby mode by programming control bits in

the control register.