TLV320AD12A

3.3-V INTEGRATED ADSL CODEC

SLWS088B – JULY 1999 – REVISED MARCH 2000

17

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

Keep-Out Zone 1

Keep-Out Zone 2

CLKIN

(35.328 MHz)

(input)

SYNC

(input)

INT

(output)

CLKOUT

(output)

SCLK

(output)

Rising edge of INT and CLKOUT occurs on fourth

rising of CLKIN after SYNC pulse is sampled high.

12

3

4

tsu2

th2

tw4

NOTE A: SYNC is used only during multicodec system-to-synchronous operation. The codec meets KOZ requirements when working alone.

Figure 3. Synchronous Pulse

tc5

tsu3

th3

tw5

tc4

th4

tsu4

td6

Hi–Z

Hi–Z

Hi–Z

Hi–Z

R/W ADR

1

ADR

0

S3

S2

S1

S0

X

D7D6

D5D4D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

R/W ADR

1

ADR

0

FS

(Input)

SCLK

(Output)

SDI

(Input)

SDO

(Output)

(Read: R/W = 1)

SDO

(Output)

(Write: R/W = 0)

See Note C

NOTES: A. Data on SDI is latched at the falling edge of SCLK.

B. Data is sent to SDO at the rising edge of SCLK.

C. ADR0 and ADR1 are the hardware configuration of ADR0 and ADR1 input pins.

Figure 4. Serial Port