TLC5618, TLC5618A

PROGRAMMABLE DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS156E – JULY 1997 – REVISED SEPTEMBER 1999

8

POST OFFICE BOX 655303

NOTE A: The input clock, applied at the SCLK terminal, should be inhibited high when CS is high to minimize clock feedthrough.

tsu(CSS)

tw(CL)

tw(CH)

CS

SCLK

DIN

tsu(DS)

th(DH)

D15

D14

D13

D12

D11

D0

ts

DAC A/B

OUT

≤ Final Value ±0.5 LSB

(see Note A)

Program Bits (4)

DAC Data

Bits (12)

tsu(CS1)

tsu(CS2)

16th Falling Edge

td(CS1)

Internally Generated

Disable at This Time

Internal

Latch

Control

(see Note A)

Figure 2. Timing Diagram for TLC5618A Only