FT4232H datasheet(20/43 Pages) FTDI

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Document No.: FT_000060

FT4232H QUAD HIGH SPEED USB TO MULTIPURPOSE UART/MPSSE IC

Datasheet Version 2.05

Clearance No.: FTDI#78

4.4

MPSSE Interface Mode Description.

MPSSE Mode is designed to allow the FT4232H to interface efficiently with synchronous serial protocols

such as JTAG, I2C and SPI Bus. It can also be used to program SRAM based FPGA’s over USB. The

MPSSE interface is designed to be flexible so that it can be configured to allow any synchronous serial

protocol (industry standard or proprietary) to be implemented using the FT4232H. MPSSE is only available

on channel A and channel B.

MPSSE is fully configurable, and is programmed by sending commands down the data stream. These can

be sent individually or more efficiently in packets. MPSSE is capable of a maximum sustained data rate of 30

Mbits/s.

When a channel is configured in MPSSE mode, the IO timing and signals used are shown in Figure 4.4 and

Table 4.1

. These show timings for CLKOUT=30MHz. CLKOUT can be divided internally to be provide a

slower clock.

Figure 4.4 MPSSE Signal Waveforms

NAME

MIN

NOM

MAX

Units

COMMENT

33.33

CLKOUT period

16.67

CLKOUT high period

16.67

CLKOUT low period

7.15

CLKOUT to TDI/DO delay

TDO/DI hold time

TDO/DI setup time

Table 4.1 MPSSE Signal Timings

MPSSE mode is enabled using Set Bit Bang Mode driver command. A hex value of 2 will enable it, and a

hex value of 0 will reset the device. See application note AN2232L-02, “Bit Mode Functions for the

FT2232D” for more details and examples.

The MPSSE command set is fully described in application note AN_108 – “Command Processor For

MPSSE and MCU Host Bus Emulation Modes”.

The following additional application notes are available for configuring the MPSSE :

•

AN_109 – “Programming Guide for High Speed FTCI2C DLL”

•

AN_110 – “Programming Guide for High Speed FTCJTAG DLL”

•

AN_111 – “Programming Guide for High Speed FTCSPI DLL”

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