TL16C554, TL16C554I

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS165D – JANUARY 1994 – REVISED JULY 1998

23

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

modem control register (MCR)

The MCR controls the interface with the modem or data set as described in Figure 16. MCR can be written and

read. The RTS and DTR outputs are directly controlled by their control bits in this register. A high input asserts

a low signal (active) at the output terminals. MCR bits 0, 1, 2, 3, and 4 are shown as follows:

high. The DTR output of the serial channel may be input into an inverting line driver in order to obtain the

proper polarity input at the modem or data set.

high. The RTS output of the serial channel may be input into an inverting line driver to obtain the proper

polarity input at the modem or data set.

serial output TXx is set to the marking (high) state and SIN is disconnected. The output of the TSR is looped

back into the RSR input. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. The

modem control outputs (DTR and RTS) are internally connected to the four modem control inputs. The

modem control output terminals are forced to their inactive (high) state on the TL16C554. In the diagnostic

mode, data transmitted is immediately received. This allows the processor to verify the transmit and receive

data paths of the selected serial channel. Interrupt control is fully operational; however, interrupts are

generated by controlling the lower four MCR bits internally. Interrupts are not generated by activity on the

external terminals represented by those four bits.

Data Terminal

Ready

0 = DTR Output Inactive (high)

1 = DTR Output Active (low)

MODEM CONTROL REGISTER

MCR

7

MCR

6

MCR

5

MCR

4

MCR

3

MCR

2

Loop

0 = Loop Disabled

1 = Loop Enabled

Bits Are Set to Logic 0

Request

to Send

0 = RTS Output Inactive (high)

1 = RTS Output Active (low)

MCR

1

MCR

0

Out1 (internal)

Out2 (internal)

No affect on external operation

0 = External Interrupt Disabled

1 = External Interrupt Enabled

Figure 16. Modem Control Register Contents