SN75LBC970A

SCSI DIFFERENTIAL CONVERTER-CONTROL

SLLS215B – MAY 1995 – REVISED JANUARY 1999

18

POST OFFICE BOX 655303

APPLICATION INFORMATION

The SCSI bus signal RST does not directly clear SDCC internal logic. Instead, the RSTFLTR terminal can be

connected as ARST – so that a bus reset clears SDCC. RSTFLTR clears the internal controller but does not clear the

RST bidirectional latch. By connecting these terminals externally through a RC filter as shown in Figure 8, noise

pulses on the bus may be filtered as recommended by the SCSI-2 specification.

SN75LBC970A

3

DSENS

6

±BSY

±SEL

±RST

8

±I/O

±MSG

±C/D

±REQ

4

±ATN

±ACK

7

4

Test

CLK40

(see Note A)

SCSI Controller

– BSY

– SEL

– I/O

– MSG

– C/D

– REQ

–ATN

– ACK

8

– RST

1

2

RESET

(From System)

VCC

TIMEOUT

55

0.022

µF

205 k

Ω

RSTFLTR

RESET

X1/CLK20

X2

DRVBUS

SDB

SN75LBC971A

16

2

8

– DB(7 – 0)

– DBP(0)

RESET

±DB(7–0)

±DBP(0)

DIFFSENS

SN75LBC971A

16

2

8

– DB(15 – 8)

– DBP(1)

RESET

±DB(15–8)

±DBP(1)

DIFFSENS

20 k

Ω

0.1 pF

BBSY

±

BSEL

±

RST

±

DIFFSENS

BI/O

±

B MSG

±

BC/D

±

BREQ

±

BATN

±

BACK

±

A BSY–

ASEL–

AI/O–

AMSG–

AC/D–

AREQ–

AATN–

AACK–

ARST –

20 MHz

(See Note A)

Optional

(See Note B)

DRVBUS

SDB

NOTES: A. When using the 40 MHz clock input, X1 must be connected to VCC.

B. The oscillator cell of the SN75LBC970A is for a series-resonant crystal and needs approximately

10 pF (including fixture capacitance) from X1 and X2 to ground in order to function.

Figure 10. Typical Application of the SN75LBC970A and SN75LBC971A