SN74ALVC126

QUADRUPLE BUS BUFFER GATE

WITH 3-STATE OUTPUTS

SCES111E – JULY 1997 – REVISED FEBRUARY 1999

1

POST OFFICE BOX 655303

CMOS) Submicron Process

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

JESD 17

Small-Outline (D), Thin Very Small-Outline

(DGV), and Thin Shrink Small-Outline (PW)

Packages

description

The SN74ALVC126 features independent line drivers with 3-state outputs. Each output is disabled when the

associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of

the driver.

The SN74ALVC126 is characterized for operation from –40

°C to 85°C.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

OE

A

Y

H

H

H

H

LL

L

X

Z

EN

1

2

1A

1Y

3

4

5

2A

2Y

6

10

9

3A

3Y

8

13

12

4A

4Y

11

1OE

2OE

3OE

4OE

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

1

Copyright

© 1999, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OE

1A

1Y

2OE

2A

2Y

GND

4OE

4A

4Y

3OE

3A

3Y

D, DGV, OR PW PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.