SN74ALS236

64

× 4

ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

SDAS107C – OCTOBER 1986 – REVISED APRIL 1998

2

POST OFFICE BOX 655303

description (continued)

The FIFO must be reset after power up with a low-level pulse on the master reset (RST) input. This sets IR high

and OR low, signifying that the FIFO is empty. Resetting the FIFO sets the outputs to a low logic level (see

Figure 1). If SI is high when RST goes high, the input data is shifted in and IR goes low and remains low until

SI goes low. If SI goes low before RST goes high, the input data is not shifted in and IR goes high. Data outputs

are noninverting with respect to the data inputs.

The SN74ALS236 is characterized for operation from 0

°C to 70°C.

Pin numbers shown are for the DW and N packages.

1D

4

D0

Q0

13

5

D1

Q1

12

6

D2

Q2

11

7

D3

Q3

10

FIFO 64

× 4

CTR

RST

3

SI

G2

R

9

OR

14

5 + /C1

15

SO

G3

4 –

IR

2

CT = 0

3CT > 0

(CT > 0) G4

2CT < 64

(CT < 64) G5

† This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.

functional block diagram

FIFO

Input

Stage

D0

D1

D2

D3

Input-

Control

Logic

IR

SI

62

× 4 Bit

Register

Register-

Control

Logic

FIFO

Output

Stage

Output-

Control

Logic

Q0

Q1

Q2

Q3

OR

SO

RST

4

5

6

7

2

3

9

13

12

11

10

15

14

Pin numbers shown are for the DW and N packages.