SN74ACT3622

256

× 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS247D – AUGUST 1993 – REVISED APRIL 1998

12

POST OFFICE BOX 655303

AEA Offset

(X2)

CLKA

RST1,

RST2

FS1, FS0

0,0

CLKB

IRB

tpd(C-IR)

4

ENA

IRA

A0 – A35

th(D)

tsu(D)

tsu(EN)

th(EN)

tsk1†

tsu(FS)

th(FS)

tpd(C-IR)

AFA Offset

(Y1)

AEB Offset

(X1)

AFB Offset

(Y2)

First Word to FIFO1

12

† tsk1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition high in the next cycle. If the time

between the rising edge of CLKA and rising edge of CLKB is less than tsk1, IRB may transition high one cycle later than shown.

NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.

Figure 2. Programming the AF Flag and AE Flag Offset Values After Reset

CLKA

IRA

CSA

W2‡

tsu(EN)

tw(CLKL)

tc

tw(CLKH)

th(EN)

th(EN)

tsu(EN)

tsu(EN)

W/RA

MBA

ENA

A0 – A35

W1‡

tsu(EN)

th(EN)

tsu(EN)

th(EN)

tsu(EN)

th(EN)

tsu(D)

th(D)

th(EN)

No Operation

‡ Written to FIFO1

Figure 3. Port-A Write-Cycle Timing for FIFO1